Ion Implantation for FinFET Devices

by Dr. Leonard Rubin, Chief Device Scientist
Axcelis Technologies, Inc.

FinFET devices were introduced in 2011 to replace planar field effect transistor (FET) devices beginning at the 22nm node (Figure 1) [1].  Following this, all core logic transistors were converted from planar to a FinFET architecture by the 16nm node in 2014 [2-4].  In its simplest form, a digital logic transistor acts as a switch.  The current flow between the source and drain terminals is either high or low depending on the controlling voltage applied to the gate. To be effective as a switch, the ratio between the current passed when the transistor is on versus when it is off must be as high as possible.  As transistors shrink, this ratio falls rapidly.  Despite their significant manufacturing challenges, FinFETs had to be introduced when this ratio for planar devices became intolerable.  In a planar transistor, only the top side (Figure 1a) of the channel (the region where the current flows between the source and the drain) is directly adjacent to the gate.  In a FinFET, the channel has been “rotated” up and onto its side so that the gate is directly adjacent to it on three out of four sides (Figure 1b).  The additional areas of proximity between the gate and the channel greatly improve the ratio of on current to off current of the FinFET device.

The transition away from planar transistors has altered the ion implantation requirements for logic devices.  Implant requirements have always been evolving with changes in transistor architecture, but the introduction of FinFETs is the biggest architecture change in over 40 years.  For example, fin-based nFET and pFET transistors on bulk silicon still require isolation of the opposite doping type (“wells”) as do planar transistors, but they are now referred to as “ground-plane” implants.  The location of these implants have moved from the bulk silicon below the isolation oxide in Figure 1a to the lower half of the fin below the oxide surface in Figure 1b.  This change was made to reduce the effect of substrate bias on FinFET transistor operation.

One of the key parameters of an nFET or pFET transistor is its threshold voltage (roughly the gate voltage at which it switches from off to on).  Modern circuits, especially those used for system-on-chip (SoC) applications [5], require 2-4 different versions of each transistor type.  Each of these transistor designs has a unique threshold voltage, which must be carefully set for the circuit to work properly.  For planar devices, this was achieved through a combination of medium current implants known as threshold voltage adjust implants. For FinFETs, the threshold voltage adjust implants are moved to an earlier position in the process flow.  In some cases, this is before the fins are etched into their final shape.

In planar devices, the source/drain extension (SDE) implants have been a major driver for the low energy and tight angle control requirements for high current implanters.  Note that SDE implants are sometimes referred to as lightly-doped-drain (LDD) implants.  In FinFET devices, the requirement for high productivity at low energies remains, while the angle control requirement increases.  For planar devices, SDE implants are usually done at zero degrees tilt.  This makes it possible to rotate the wafer between implant segments to partially average out any non-uniformity in the implanter’s scanning system or ribbon beam optics.  For FinFET devices, the SDE implants are done at tilt angles up to 35 degrees.  Wafer rotation is now required instead of optional, and the implanter uniformity requirements for each rotation step increases significantly.  Additionally, SDE implants cause amorphization of the silicon crystal in the channel region.  This is tolerable for planar devices, but is problematic for FinFETs because the narrow fin extends above the substrate (Fig. 1b).  The problem is especially severe for the n-type FinFET, because the arsenic used for the nFET SDE causes much more crystal damage than the boron used for pFET SDE implants.   One potential solution to this is to heat the wafer during the SDE implant, as this will minimize or prevent amorphization.  Implant temperatures as high as 450-500°C are being considered for this application [6].

The parasitic resistance of the contacts between the first metal layer and the source/drain region has been increasing due to the shrinking area available for these contacts.  This problem exists for planar devices but is more severe for FinFET devices due to their vertical geometry.  High dose, low energy, contact implants are used to help minimize contact resistance.  These implants often consist of a sequence of dopant and non-dopant (“materials modification”) implants.  Phosphorus and boron are used to ensure that the contact region is heavily doped, while carbon and nitrogen are the most commonly used non-dopant species.  Because the contact region is at the bottom of a high aspect ratio rectangular hole in an insulating layer, proper angle control is of paramount importance for optimizing the contact resistance.

The use of materials modification implants in FinFET devices is not limited to the contact structure.  Non-dopant implants are used for purposes such as modifying the etch rate of various films and stabilizing photoresist layers.  The increasing count of these new implants has expanded the number of species that ion sources need to handle while maintaining high source life.

Despite these differences between planar and FinFET, some aspects of transistor manufacturing remain relatively unchanged.  Firstly, both transistor types are manufactured primarily, but not exclusively, on bulk silicon substrates.  The remaining small fraction use silicon-on-insulator (SOI) substrates.  Despite the lower power consumption and process simplicity provided by SOI substrates, bulk silicon substrates dominate because SOI wafers are about 3X more expensive than bulk silicon wafers.  The continued dominance of bulk silicon is fortunate for the ion implant industry, as bulk silicon processes require many more implants than SOI silicon processes.  Secondly, advanced transistors of both the planar and the FinFET variety use gates made of metal (as opposed to polycrystalline silicon) and gate dielectrics made of high-k perovskite materials (as opposed to silicon oxynitride).  The fine tuning of the electrical properties of the metal gates and the insulating properties of the gate dielectrics provide additional opportunities for ion implantation.

The new challenges of FinFET manufacturing require that implanters deliver higher beam currents at lower energies and better angle control, while also providing the reliability, particulate control, and metals control that all advanced devices require.

Figure 1

Figure 1: Graphical representation of a planar transistor (a) and a FinFET (b).  From Ref. 7.


[1] C.-H. Jan, et al., “A 22nm SoC Platform Technology Featuring 3-D Tri-Gate and High-k/Metal Gate, Optimized for Ultra Low Power, High Performance and High Density SoC Applications”, Proc. IEDM (2012) pp. 44-47.

[2] S.-Y. Wu, et al., “An Enhanced 16nm CMOS Technology Featuring 2nd Generation FinFET Transistors and Advanced Cu/low-k Interconnect for Low Power and High Performance Applications”, Proc. IEDM (2014) pp. 48-51.

[3] S. Natarajan, “A 14nm Logic Technology Featuring 2nd-Generation FinFET , Air-Gapped Interconnects, Self-Aligned Double Patterning and a 0.0588 µm2 SRAM cell size”, Proc. IEDM (2014) pp. 71-73.

[4] C-H. Lin, et al., “High Performance 14nm SOI FinFET CMOS Technology with 0.0174μm2 embedded DRAM and 15 Levels of Cu Metallization”, Proc. IEDM (2014) pp. 74-76.

[5] T. Miyashita, et al., “High Voltage I/O FinFET Device Optimization for 16nm System-on-a-Chip (SoC) Technology”, Proc. Symp. VLSI Tech., (2015) pp. T152-T153.

[6] L. C. Pipes, et al., “NMOS Source-drain Extension Ion Implantation into Heated Substrates”, Proc. XXIntl. Conf. Ion Implant. Tech., (2014) pp. 37-42.