The Importance of Threshold Control in Advanced Devices

by Dr. Leonard Rubin, Cheif Device Scientist

As device size and supply voltages shrink and device density increases, the required precision of the dopant placement also increases.  This is true for almost all transistor and circuit types, but is especially important for circuits that rely on matched pairs of transistors to operate.  Two very widely used examples of circuitry requiring matched transistor pairs are the DRAM sense-amplifier (SA) and the SRAM memory cell used in microprocessor cache memory and other logic applications.  Successful fabrication of these circuit types in advanced nodes requires the best available precision in implant energy, dose, and most importantly, beam angle.

The DRAM sense-amplifier (Figure 1) is needed for both reading and writing the bit state on the capacitive storage element in the DRAM cell.  It must detect and amplify the extremely weak output of the storage capacitor, and also amplify the write signal to the capacitor during programming or after a destructive read operation.  From the symmetry of the cross-connected pairs (latch devices) of nFET and pFET transistors at the center of the amplifier, it is clear that any mismatch in transistor performance will produce an offset voltage in SAN from the ideal VDD/2.  Compensating for this will require increased circuit margins, resulting in reduced sensitivity for the amplifier [1,2].  Decreasing supply voltages mean that an ever-larger percentage of the supply voltage will be consumed by the SA operational margin unless it can be proportionally reduced.

The architecture of a standard six transistor (6T) SRAM cell (Figure 2) is conceptually similar to that of a DRAM sense-amplifier.  The cell consists of two CMOS inverters cross-latched to each other, connected to the rest of the circuit by two nFET access transistors.  The cross-latched inverters result in a bi-stable cell that holds one bit of memory until the cell is reprogrammed or the power is disconnected.  In practice, the memory state is only preserved as long as circuit noise does not exceed the static noise margin (SNM) of the cell.  A 6T SRAM cell has three separate SNM values, for data retention, reading, and writing [4].  Ideally, all of these SNM values should be as high as possible, approaching the ideal value of VDD/2.  As VDD decreases, the SNM will decrease proportionally unless transistor improvements are implemented to increase SNM relative to VDD/2.  Typically it is the write SNM that is the most challenging to maximize.  As is the case with DRAM sense-amplifier, optimum SRAM performance (maximizing SNM) requires that the device symmetry indicated in the circuit schematic be replicated in the actual performance of the individual transistors [5,6].

For both the DRAM SA and the SRAM cell, optimum performance requires transistors with good ION, IOFF, and most importantly, threshold voltage.  The threshold voltage is the most critical transistor parameter to be matched.  All of the nFETs in each cell and all of the pFETs in each cell should have VT values as close as possible.  (The VT values of the nFETs and pFETs should properly complement each other, but this is easier to achieve because the nFETs and pFETs are adjusted independently.)  This level of equivalency and symmetry then needs to be replicated across every cell or amplifier on the die, every die on the wafer, every wafer in the lot, and so on.

Figure 1: DRAM sense amplifier

Figure 1:  DRAM sense amplifier.  (a) schematic, showing bitlines, wordline, sense lines, select line, and input/output.  (b) partial top-down circuit view

Figure 2: SRAM 6T cell

Figure 2:  SRAM 6T cell.  (a) schematic, showing bitlines, and wordline. 
(b) top-down circuit view of a 22nm device. Reference [3].

It is well known that threshold voltage values depend on many process steps, including lithography, deposition, and etch, but the most important process is ion implantation.  Implants into the channel, halo, extension, polysilicon (if present), and source/drain regions can all affect the threshold voltage of the device.  For each implant, energy, dose, and beam angle are (at a minimum) critical factors.  Because die sizes are smaller than typical beam dimensions, implant energy and dose are almost always uniform across the die (but not necessarily across the wafer or across the lot).   Because adjacent transistors in the cell have different orientations (Figs. 1b,2b), any errors in beam angle for the implants mentioned above will negatively affect VT uniformity and therefore circuit performance.  Figure 3 shows several examples of systematic doping variations possible from ion implant variations with other process steps.  Uncontrolled variations in ion beam angle will only exacerbate these issues.  For this reason, the entire suite of Axcelis implanters (Optima HDx, Purion M, and Purion XE) all offer in situ angle measurement and control to minimize angle errors.Figure 3: Non-random mismatch SRAM cells

Figure 3:  Depiction of four alignment sensitive sources of non-random mismatch in SRAM cells. (a) lateral straggle with in SiO2, (b) lateral counterdoping in gate polysilicon, (c) lateral straggle from resist sidewall, (d) halo shadowing.  Reference [5].

The advantages provided by Axcelis implanters are largest in the high current space, where the differences in scanning architecture vs. competitive offerings are most pronounced.  Only the Optima HDx offers 2D mechanical scanning, ensuring that every point on the wafer sees the exact same beam, in terms of dose, beam density, and angular distribution.  Fixed beam systems with 1D scanning are unable to compensate for horizontal variations across the beam in any of these parameters.  Several manufacturers have reported to Axcelis that 2D mechanical scanning noticeably improved DRAM SA sensitivity and SRAM SNM for advanced devices over those from high current implants using 1D scanning.  These advantages are expected to increase as SA and SNM requirements continue to be tightened.



[1]    B. S. Kiyoo Itoh, et al., “Limitations and challenges of multigigabit DRAM chip design”, IEEE Journal of Solid-State Circuits, v. 32 no 5 (1997) pp. 624-634.

[2]    S. A. Parke, “Optimization of DRAM sense amplifiers for the gigabit era”, Proceedings of the 40th Midwest Symposium on Circuits and Systems, v. 1 (1997) pp. 209-212.

[3]    B. S. Haran, et al., “22 nm Technology Compatible Fully Functional 0.1 μm2 6T-SRAM Cell”, Proc. IEDM, (2008) pp. 625-628.

[4]    B. H. Calhoun, et al., “Static Noise Margin Variation for Sub-threshold SRAM in 65-nm CMOS”, IEEE Journal of Solid-State Circuits, v. 41, no. 7, (2006) pp. 1673-1679.

[5]    R. W. Mann, et al., “Nonrandom Device Mismatch Considerations in Nanoscale SRAM”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v. 20 no. 7 (2012) pp. 1211-1220.

[6]    E. Morifuji, et al., “Supply and Threshold-Voltage Trends for Scaled Logic and SRAM MOSFETs”, IEEE Transactions on Electron Devices, v. 53, no. 6, (2006) pp. 1427-1432.