Impact of Wafer Cleaning on Intra- and Inter-Die Non-Uniformity

by Ivan Berry, Director of Technology, Cleaning

Much effort is placed on understanding and controlling process variability as it impacts statistical device-to-device performance. At the gate level, tight controls are placed on lithography, etch, implantation and anneal for example, to produce tight transistor performance distributions. Wafer cleaning can also induce systematic and pseudo-random process variations that can have significant impact on performance. One of the more significant variables is how cleaning steps can induce sidewall spacer thickness changes. Data presented in a paper by IBM for a 65nm process flow shows that transistor drive current can change by more than 1% for every angstrom variation in sidewall spacer thickness[i].

Silicon Nitride spacers, especially after ion implantation damage, are etched by strong acids such as sulfuric acid, commonly used in post ion implantation cleans. This etch rate is modulated by changes in spacer density, hydrogen bond density, implantation damage, and local proximity effects. The 2011 ITRS roadmap points out that because etch rate variability can be significant, total nitride spacer loss needs to be 0.1Å or less for the complete photoresist strip and clean. At the Device level, the gate edge capacitance (Cge) can be used to monitor the spacer thickness variation as this capacitance is modulated by the spacer thickness.  (A larger capacitance corresponds to more spacer thickness loss).  The figure below shows some across-die Cge measurements for 3 different post ion implantation clean sequences. The largest variation, also the most spacer loss, occurs for a hot sulfuric acid clean (5 minutes, at 180C).  This variation equates to about 4Å. A standard O2+FG (Forming Gas) strip followed by an SPM/APM clean yields an equivalent spacer width variation of about 2Å, while the Axcelis COD clean (Controlled Oxygen Diffusion, a non-oxidizing, hot gas cleaning process) followed by a mild acid/base clean results in lower total spacer loss, and a very tight distribution with an equivalent loss variation <1Å.

The Axcelis COD resist stripping process utilizes a hot gas for removal of any organic materials and is very effective at removing ion implanted resist with almost no post strip residues.  As the impacts on device performance of resist removal processes become increasingly important, the COD processes running on the Axcelis Integra ES should be considered by advanced transistor manufacturers as an alternative to traditional processes.  For more information on the unique Axcelis COD process, download a free copy of a whitepaper on this topic.

[i] A. Bansal, et. al. IEEE Trans. Electron Devices, 55, 5, 2008